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Production-proven Through Silicon Via Chemistries Meet High Aspect Ratio Requirements
Years of experience and success in electroplating damascene copper have helped DuPont Electronics & Imaging bring leading-edge copper through silicon via (TSV) chemistries to the advanced packaging market. Our production-proven, three-component copper solutions enable even the most challenging TSV aspect ratios due to:
- High purity copper
- Gap-free performance during bottom-up fill
- Fast plating speeds
- Elimination of Cu overburden
As TSVs become a mainstream interconnect technology used in memory stacking, CMOS image sensors, MEMS devices, and 2.5D interposer architectures, DuPont remains at the forefront, optimizing offerings to meet TSVs evolving needs.
Product Lines
- Interlink™ 9200 Copper
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What is TSV Technology?
Through silicon vias (TSVs) are vertical electrical interconnects formed using wafer etch processes and filled with either Cu or tungsten. First introduced in compound semiconductor applications, TSVs are also used in MEMS devices and CMOS image sensors, to create 3D memory stacks, and 2.5D interposer architectures, driven by high-performance computing needs.
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Copper for High-Aspect-Ratio Vias
Our Cu chemistries for TSV production are designed to meet requirements for leading edge TSVs with a 10:1 aspect ratio. This requires high purity, faster plating speeds without voids, gap-free bottom-up fill with minimal Cu overburden to reduce the need for chemical mechanical planarization processes.
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Our Semiconductor Packaging Portfolio
DuPont delivers a full portfolio of packaging and assembly materials for the semiconductor industry. Click here to view a short video of our comprehensive offerings.
Semiconductor Packaging Materials
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Through Silicon Via Copper
Through Silicon Via Copper
Years of experience and success in electroplating damascene copper have helped DuPont bring leading-edge copper TSV chemistries to the advanced packaging market.
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View DetailsHVM-proven tin-silver plating chemistry for lead-free, fine-pitch solder bump applications with industry-leading process versatility. -
Under Bump Metallization
Under Bump Metallization
We offer a production-proven electroplating nickel chemistry tailored to meet a variety of UBM process needs
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View DetailsWafer-level packaging dry-film photoresist solutions for 3DIC, fan out, bumping, copper pillar and redistribution applications.DuPont offers liquid bump plating photoresists, along with associated ancillaries, that are ideally suited for wafer-level packaging applications using single-spin coating. -
Copper Redistribution Layer
Copper Redistribution Layer
DuPont Electronics & Imaging copper chemistries for redistribution layers (RDLs) are ideally suited to today’s high-density requirements for wafer level packaging applications.
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Packaging Dielectrics
Packaging Dielectrics
Look to DuPont for packaging dielectric formulations that have the mechanical properties, high resolution, low-temp curing, easy processes, and superior reliability needed to protect your advanced WLP.
View Details